Memory transistors with a dielectric storage layer sequence are usually embodied as planar transistors or as trench transistors. The structure of these transistors therefore corresponds to the structure of standard NMOS transistors. In this case, the gate dielectric is replaced by a storage layer sequence comprising a storage layer between boundary layers, in which charge carriers from the channel are trapped during the programming of the memory cell. With this memory cell construction, the problem arises that, owing to the required data retention (retention time) and sufficiently high number of programming/erasure cycles, the thicknesses of the dielectric layers are relatively large compared with the gate oxide of conventional transistors. By way of example, use is made of storage layer sequences comprising a channel-side bottom oxide having a typical thickness of 6 nm, a silicon nitride storage layer having a thickness of typically 6 nm and a top oxide on the side of the gate electrode having a thickness of typically 12 nm. The disadvantages of such a thick gate dielectric are a poor gate control, associated with a poor slope of the control curve, a high threshold voltage and an unfavorable scalability.
The publication by T. Park et al.: “Fabrication of Body-Tied FinFETs (Omega MOSFETS) Using Bulk Si Wafers”, 2003 Symposium on VLSI Technology Digest of Technical Papers (June 2003), describes DRAM cell transistors in which the channel is present in a rib active region which is spanned in bridge-like fashion or encompassed in pincers-like fashion by the gate electrode. The upper portion of the channel region is rounded due to the dictates of fabrication, which is regarded as an advantage owing to the resultant suppression of undesirable leakage currents along the essentially planar side channels.